Performance Study of 4:1 Multiplexer CMOS Logic Structures

Now days, low power and low energy have become an important issue in consumer electronics and it is necessary to do research in combinational circuits. One of the important elements in digital circuits is a multiplexer or data selector for processing multiple inputs with a single output. Presently, multiplexers have become a universal logic element used to design any digital combinational logic circuits /systems in IC’s, so it is needed to design or revise a multiplexer topology for low power consumption and high speed. In this paper, the different designs of multiplexer using complementary metal oxide semiconductor (CMOS) logic are analyzed in performance point of view. The multiplexer structures are realized using Positive Feedback Adiabatic Logic (PFAL), Cascode Voltage Switch Logic (CVSL) and Transmission Gate Based logic styles. The power consumption, delay, supply voltage and number of transistors present in the designs are tabulated and compared. The performance study is carried out using 0.18-μm CMOS technology. These different logic styles are differentiated by performing detailed transistor level simulations using CAD tools of DSCH3 and Micro wind 3.1.